<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>CPTR_EL2</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CPTR_EL2, Architectural Feature Trap Register (EL2)</h1><p>The CPTR_EL2 characteristics are:</p><h2>Purpose</h2>
        <p>Controls trapping to EL2 of accesses to <a href="AArch32-cpacr.html">CPACR</a>, <a href="AArch64-cpacr_el1.html">CPACR_EL1</a>, trace, Activity Monitor, 
SME, Streaming SVE, 
SVE, 
and Advanced SIMD and floating-point functionality.</p>
      <h2>Configuration</h2><p>AArch64 System register CPTR_EL2 bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-hcptr.html">HCPTR[31:0]</a>.</p>
        <p>If EL2 is not implemented, this register is <span class="arm-defined-word">RES0</span> from EL3.</p>

      
        <p>This register has no effect if EL2 is not enabled in the current Security state.</p>
      <h2>Attributes</h2>
        <p>CPTR_EL2 is a 64-bit register.</p>
      <h2>Field descriptions</h2><h3>When FEAT_VHE is implemented and HCR_EL2.E2H == 1:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_32">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">TCPAC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_30-1">TAM</a></td><td class="lr" colspan="1"><a href="#fieldset_0-29_29-1">E0POE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-28_28">TTA</a></td><td class="lr" colspan="2"><a href="#fieldset_0-27_26">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-25_24-1">SMEN</a></td><td class="lr" colspan="2"><a href="#fieldset_0-23_22">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-21_20">FPEN</a></td><td class="lr" colspan="2"><a href="#fieldset_0-19_18">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-17_16-1">ZEN</a></td><td class="lr" colspan="16"><a href="#fieldset_0-15_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-63_32">Bits [63:32]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_31">TCPAC, bit [31]</h4><div class="field"><p>In AArch64 state, traps accesses to <a href="AArch64-cpacr_el1.html">CPACR_EL1</a> from EL1 to EL2, when EL2 is enabled in the current Security state. The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x18</span>.</p>
<p>In AArch32 state, traps accesses to <a href="AArch32-cpacr.html">CPACR</a> from EL1 to EL2, when EL2 is enabled in the current Security state. The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x03</span>.</p><table class="valuetable"><tr><th>TCPAC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>EL1 accesses to <a href="AArch64-cpacr_el1.html">CPACR_EL1</a> and <a href="AArch32-cpacr.html">CPACR</a> are trapped to EL2, when EL2 is enabled in the current Security state.</p>
        </td></tr></table><p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 1, this control does not cause any instructions to be trapped.</p>
<div class="note"><span class="note-header">Note</span><p><a href="AArch64-cpacr_el1.html">CPACR_EL1</a> and <a href="AArch32-cpacr.html">CPACR</a> are not accessible at EL0.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-30_30-1">TAM, bit [30]<span class="condition"><br/>When FEAT_AMUv1 is implemented:
                        </span></h4><div class="field"><p>Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL2, as follows:</p>
<ul>
<li>
<p>In AArch64 state, accesses to the following registers are trapped to EL2, reported using ESR_ELx.EC value <span class="hexnumber">0x18</span>:</p>
<ul>
<li><a href="AArch64-amuserenr_el0.html">AMUSERENR_EL0</a>, <a href="AArch64-amcfgr_el0.html">AMCFGR_EL0</a>, <a href="AArch64-amcgcr_el0.html">AMCGCR_EL0</a>, <a href="AArch64-amcntenclr0_el0.html">AMCNTENCLR0_EL0</a>, <a href="AArch64-amcntenclr1_el0.html">AMCNTENCLR1_EL0</a>, <a href="AArch64-amcntenset0_el0.html">AMCNTENSET0_EL0</a>, <a href="AArch64-amcntenset1_el0.html">AMCNTENSET1_EL0</a>, <a href="AArch64-amcr_el0.html">AMCR_EL0</a>, <a href="AArch64-amevcntr0n_el0.html">AMEVCNTR0&lt;n&gt;_EL0</a>, <a href="AArch64-amevcntr1n_el0.html">AMEVCNTR1&lt;n&gt;_EL0</a>, <a href="AArch64-amevtyper0n_el0.html">AMEVTYPER0&lt;n&gt;_EL0</a>, and <a href="AArch64-amevtyper1n_el0.html">AMEVTYPER1&lt;n&gt;_EL0</a>.
</li></ul>

</li><li>
<p>In AArch32 state, MRC or MCR accesses to the following registers are trapped to EL2 and reported using ESR_ELx.EC value <span class="hexnumber">0x03</span>:</p>
<ul>
<li><a href="AArch32-amuserenr.html">AMUSERENR</a>, <a href="AArch32-amcfgr.html">AMCFGR</a>, <a href="AArch32-amcgcr.html">AMCGCR</a>, <a href="AArch32-amcntenclr0.html">AMCNTENCLR0</a>, <a href="AArch32-amcntenclr1.html">AMCNTENCLR1</a>, <a href="AArch32-amcntenset0.html">AMCNTENSET0</a>, <a href="AArch32-amcntenset1.html">AMCNTENSET1</a>, <a href="AArch32-amcr.html">AMCR</a>, <a href="AArch32-amevtyper0n.html">AMEVTYPER0&lt;n&gt;</a>, and <a href="AArch32-amevtyper1n.html">AMEVTYPER1&lt;n&gt;</a>.
</li></ul>

</li><li>
<p>In AArch32 state, MRRC or MCRR accesses to <a href="AArch32-amevcntr0n.html">AMEVCNTR0&lt;n&gt;</a> and <a href="AArch32-amevcntr1n.html">AMEVCNTR1&lt;n&gt;</a>, are trapped to EL2, reported using ESR_ELx.EC value <span class="hexnumber">0x04</span>.</p>

</li></ul><table class="valuetable"><tr><th>TAM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Accesses from EL1 and EL0 to Activity Monitor registers are not trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2, when EL2 is enabled in the current Security state.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-30_30-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-29_29-1">E0POE, bit [29]<span class="condition"><br/>When FEAT_S1POE is implemented:
                        </span></h4><div class="field"><p>Enable access to <a href="AArch64-por_el0.html">POR_EL0</a>.</p>
<p>Traps EL0 accesses to <a href="AArch64-por_el0.html">POR_EL0</a> to EL2, from AArch64 state only. The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x18</span>.</p><table class="valuetable"><tr><th>E0POE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control causes EL0 access to <a href="AArch64-por_el0.html">POR_EL0</a> to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-29_29-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-28_28">TTA, bit [28]</h4><div class="field"><p>Traps System register accesses to all implemented trace registers from both Execution states to EL2, when EL2 is enabled in the current Security state, as follows:</p>
<ul>
<li>
<p>In AArch64 state, accesses to trace registers with op0=2, op1=1, and CRn&lt;<span class="binarynumber">0b1000</span> are trapped to EL2, reported using EC syndrome value <span class="hexnumber">0x18</span>.</p>

</li><li>
<p>In AArch32 state, MRC or MCR accesses to trace registers with cpnum=14, opc1=1, and CRn&lt;<span class="binarynumber">0b1000</span> are trapped to EL2, reported using EC syndrome value <span class="hexnumber">0x05</span>.</p>

</li></ul><table class="valuetable"><tr><th>TTA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Any attempt at EL0, EL1 or EL2, to execute a System register access to an implemented trace register is trapped to EL2, when EL2 is enabled in the current Security state, unless <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 0 and it is trapped by <a href="AArch32-cpacr.html">CPACR</a>.NSTRCDIS or <a href="AArch64-cpacr_el1.html">CPACR_EL1</a>.TTA.</p>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 1, any attempt at EL0 or EL2 to execute a System register access to an implemented trace register is trapped to EL2, when EL2 is enabled in the current Security state.</p></td></tr></table><div class="note"><span class="note-header">Note</span><p>The ETMv4 architecture and ETE do not permit EL0 to access the trace registers. If the trace unit implements FEAT_ETMv4 or ETE, EL0 accesses to the trace registers are <span class="arm-defined-word">UNDEFINED</span>, and any resulting exception is higher priority than an exception that would be generated because the value of CPTR_EL2.TTA is 1.</p><p>EL2 does not provide traps on trace register accesses through the optional Memory-mapped interface.</p></div><p>System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.</p>
<p>If System register access to the trace functionality is not supported, this bit is <span class="arm-defined-word">RES0</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-27_26">Bits [27:26]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-25_24-1">SMEN, bits [25:24]<span class="condition"><br/>When FEAT_SME is implemented:
                        </span></h4><div class="field"><p>Traps execution at EL2, EL1, and EL0 of SME instructions, SVE instructions when FEAT_SVE is not implemented or the PE is in Streaming SVE mode, and instructions that directly access the <a href="AArch64-svcr.html">SVCR</a>, <a href="AArch64-smcr_el1.html">SMCR_EL1</a>, or <a href="AArch64-smcr_el2.html">SMCR_EL2</a> System registers to EL2, when EL2 is enabled in the current Security state.</p>
<p>When instructions that directly access the <a href="AArch64-svcr.html">SVCR</a> System register are trapped with reference to this control, the <span class="instruction">MSR SVCRSM</span>, <span class="instruction">MSR SVCRZA</span>, and <span class="instruction">MSR SVCRSMZA</span> instructions are also trapped.</p>
<p>The exception is reported using ESR_EL2.EC value of <span class="hexnumber">0x1D</span>, with an ISS code of <span class="hexnumber">0x0000000</span>.</p>
<p>This field does not affect whether Streaming SVE or SME register values are valid.</p>
<p>A trap taken as a result of CPTR_EL2.SMEN has precedence over a trap taken as a result of CPTR_EL2.FPEN.</p><table class="valuetable"><tr><th>SMEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td><p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 0, this control does not cause execution of any instructions to be trapped.</p>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 1, this control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL2 to be trapped.</p></td></tr><tr><td class="bitfield">0b10</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>This control does not cause execution of any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-25_24-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-23_22">Bits [23:22]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-21_20">FPEN, bits [21:20]</h4><div class="field"><p>Traps execution at EL2, EL1, and EL0 of instructions that access the Advanced SIMD and floating-point registers from both Execution states to EL2, when EL2 is enabled in the current Security state. The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x07</span>.</p>
<p>Traps execution at EL2, EL1, and EL0 of 
SME and 
SVE instructions 
 to EL2, when EL2 is enabled in the current Security state.
The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x07</span>.</p>
<p>A trap taken as a result of CPTR_EL2.SMEN has precedence over a trap taken as a result of CPTR_EL2.FPEN.</p>
<p>A trap taken as a result of CPTR_EL2.ZEN has precedence over a trap taken as a result of CPTR_EL2.FPEN.</p><table class="valuetable"><tr><th>FPEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td><p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 0, this control does not cause execution of any instructions to be trapped.</p>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 1, this control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL2 to be trapped.</p></td></tr><tr><td class="bitfield">0b10</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>This control does not cause execution of any instructions to be trapped.</p>
        </td></tr></table><p>Writes to <a href="AArch32-mvfr0.html">MVFR0</a>, <a href="AArch32-mvfr1.html">MVFR1</a>, and <a href="AArch32-mvfr2.html">MVFR2</a> from EL1 or higher are <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> and whether these accesses can be trapped by this control depends on implemented <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> behavior.</p>
<div class="note"><span class="note-header">Note</span><ul><li>Attempts to write to the FPSID count as use of the registers for accesses from EL1 or higher.</li><li>Accesses from EL0 to <a href="AArch32-fpsid.html">FPSID</a>, <a href="AArch32-mvfr0.html">MVFR0</a>, <a href="AArch32-mvfr1.html">MVFR1</a>, <a href="AArch32-mvfr2.html">MVFR2</a>, and <a href="AArch32-fpexc.html">FPEXC</a> are <span class="arm-defined-word">UNDEFINED</span>, and any resulting exception is higher priority than an exception that would be generated because the value of CPTR_EL2.FPEN is not <span class="binarynumber">0b11</span>.</li></ul></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-19_18">Bits [19:18]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-17_16-1">ZEN, bits [17:16]<span class="condition"><br/>When FEAT_SVE is implemented:
                        </span></h4><div class="field"><p>Traps execution at EL2, EL1, and EL0 of SVE instructions when the PE is not in Streaming SVE mode, and instructions that directly access the <a href="AArch64-zcr_el1.html">ZCR_EL1</a> or <a href="AArch64-zcr_el2.html">ZCR_EL2</a> System registers to EL2, when EL2 is enabled in the current Security state.</p>
<p>The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x19</span>.</p>
<p>A trap taken as a result of CPTR_EL2.ZEN has precedence over a trap taken as a result of CPTR_EL2.FPEN.</p><table class="valuetable"><tr><th>ZEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td><p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 0, this control does not cause execution of any instructions to be trapped.</p>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 1, this control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL2 to be trapped.</p></td></tr><tr><td class="bitfield">0b10</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>This control does not cause execution of any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-17_16-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_0">Bits [15:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h3>Otherwise:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-63_32">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_1-31_31">TCPAC</a></td><td class="lr" colspan="1"><a href="#fieldset_1-30_30-1">TAM</a></td><td class="lr" colspan="9"><a href="#fieldset_1-29_21">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-20_20">TTA</a></td><td class="lr" colspan="6"><a href="#fieldset_1-19_14">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-13_13">RES1</a></td><td class="lr" colspan="1"><a href="#fieldset_1-12_12-1">TSM</a></td><td class="lr" colspan="1"><a href="#fieldset_1-11_11">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-10_10">TFP</a></td><td class="lr" colspan="1"><a href="#fieldset_1-9_9">RES1</a></td><td class="lr" colspan="1"><a href="#fieldset_1-8_8-1">TZ</a></td><td class="lr" colspan="8"><a href="#fieldset_1-7_0">RES1</a></td></tr></tbody></table><div class="text_before_fields">
    <p>This format applies in all Armv8.0 implementations.</p>
  </div><h4 id="fieldset_1-63_32">Bits [63:32]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-31_31">TCPAC, bit [31]</h4><div class="field"><p>In AArch64 state, traps accesses to <a href="AArch64-cpacr_el1.html">CPACR_EL1</a> from EL1 to EL2, when EL2 is enabled in the current Security state. The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x18</span>.</p>
<p>In AArch32 state, traps accesses to <a href="AArch32-cpacr.html">CPACR</a> from EL1 to EL2, when EL2 is enabled in the current Security state. The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x03</span>.</p><table class="valuetable"><tr><th>TCPAC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>EL1 accesses to the following registers are trapped to EL2, when EL2 is enabled in the current Security state:</p>
<ul>
<li><a href="AArch64-cpacr_el1.html">CPACR_EL1</a>.
</li><li><a href="AArch32-cpacr.html">CPACR</a>.
</li></ul></td></tr></table><p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE is 1, this control does not cause any instructions to be trapped.</p>
<div class="note"><span class="note-header">Note</span><p><a href="AArch64-cpacr_el1.html">CPACR_EL1</a> and <a href="AArch32-cpacr.html">CPACR</a> are not accessible at EL0.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-30_30-1">TAM, bit [30]<span class="condition"><br/>When FEAT_AMUv1 is implemented:
                        </span></h4><div class="field"><p>Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL2, as follows:</p>
<ul>
<li>
<p>In AArch64 state, accesses to the following registers are trapped to EL2, reported using ESR_ELx.EC value <span class="hexnumber">0x18</span>:</p>
<ul>
<li><a href="AArch64-amuserenr_el0.html">AMUSERENR_EL0</a>, <a href="AArch64-amcfgr_el0.html">AMCFGR_EL0</a>, <a href="AArch64-amcgcr_el0.html">AMCGCR_EL0</a>, <a href="AArch64-amcntenclr0_el0.html">AMCNTENCLR0_EL0</a>, <a href="AArch64-amcntenclr1_el0.html">AMCNTENCLR1_EL0</a>, <a href="AArch64-amcntenset0_el0.html">AMCNTENSET0_EL0</a>, <a href="AArch64-amcntenset1_el0.html">AMCNTENSET1_EL0</a>, <a href="AArch64-amcr_el0.html">AMCR_EL0</a>, <a href="AArch64-amevcntr0n_el0.html">AMEVCNTR0&lt;n&gt;_EL0</a>, <a href="AArch64-amevcntr1n_el0.html">AMEVCNTR1&lt;n&gt;_EL0</a>, <a href="AArch64-amevtyper0n_el0.html">AMEVTYPER0&lt;n&gt;_EL0</a>, and <a href="AArch64-amevtyper1n_el0.html">AMEVTYPER1&lt;n&gt;_EL0</a>.
</li></ul>

</li><li>
<p>In AArch32 state, MCR or MRC accesses to the following registers are trapped to EL2 and reported using ESR_ELx.EC value <span class="hexnumber">0x03</span>:</p>
<ul>
<li><a href="AArch32-amuserenr.html">AMUSERENR</a>, <a href="AArch32-amcfgr.html">AMCFGR</a>, <a href="AArch32-amcgcr.html">AMCGCR</a>, <a href="AArch32-amcntenclr0.html">AMCNTENCLR0</a>, <a href="AArch32-amcntenclr1.html">AMCNTENCLR1</a>, <a href="AArch32-amcntenset0.html">AMCNTENSET0</a>, <a href="AArch32-amcntenset1.html">AMCNTENSET1</a>, <a href="AArch32-amcr.html">AMCR</a>, <a href="AArch32-amevtyper0n.html">AMEVTYPER0&lt;n&gt;</a>, and <a href="AArch32-amevtyper1n.html">AMEVTYPER1&lt;n&gt;</a>.
</li></ul>

</li><li>
<p>In AArch32 state, MCRR or MRRC accesses to <a href="AArch32-amevcntr0n.html">AMEVCNTR0&lt;n&gt;</a> and <a href="AArch32-amevcntr1n.html">AMEVCNTR1&lt;n&gt;</a>, are trapped to EL2, reported using ESR_ELx.EC value <span class="hexnumber">0x04</span>.</p>

</li></ul><table class="valuetable"><tr><th>TAM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Accesses from EL1 and EL0 to Activity Monitor registers are not trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2, when EL2 is enabled in the current Security state.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-30_30-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-29_21">Bits [29:21]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-20_20">TTA, bit [20]</h4><div class="field"><p>Traps System register accesses to all implemented trace registers from both Execution states to EL2, when EL2 is enabled in the current Security state, as follows:</p>
<ul>
<li>
<p>In AArch64 state, accesses to trace registers with op0=2, op1=1, and CRn&lt;<span class="binarynumber">0b1000</span> are trapped to EL2, reported using EC syndrome value <span class="hexnumber">0x18</span>.</p>

</li><li>
<p>In AArch32 state, MRC or MCR accesses to trace registers with cpnum=14, opc1=1, and CRn&lt;<span class="binarynumber">0b1000</span> are trapped to EL2, reported using EC syndrome value <span class="hexnumber">0x05</span>.</p>

</li></ul><table class="valuetable"><tr><th>TTA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Any attempt at EL0, EL1, or EL2, to execute a System register access to an implemented trace register is trapped to EL2, when EL2 is enabled in the current Security state, unless it is trapped by one of the following controls:</p>
<ul>
<li><a href="AArch64-cpacr_el1.html">CPACR_EL1</a>.TTA.
</li><li><a href="AArch32-cpacr.html">CPACR</a>.TRCDIS.
</li></ul></td></tr></table><div class="note"><span class="note-header">Note</span><ul><li>The ETMv4 architecture does not permit EL0 to access the trace registers. If the trace unit implements FEAT_ETMv4, EL0 accesses to the trace registers are <span class="arm-defined-word">UNDEFINED</span>, and any resulting exception is higher priority than an exception that would be generated because the value of <a href="AArch64-cptr_el2.html">CPTR_EL2</a>.TTA is 1.</li><li>EL2 does not provide traps on trace register accesses through the optional memory-mapped interface.</li></ul></div><p>System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.</p>
<p>If System register access to the trace functionality is not supported, this bit is <span class="arm-defined-word">RES0</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-19_14">Bits [19:14]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-13_13">Bit [13]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_1-12_12-1">TSM, bit [12]<span class="condition"><br/>When FEAT_SME is implemented:
                        </span></h4><div class="field"><p>Traps execution at EL2, EL1, and EL0 of SME instructions, SVE instructions when FEAT_SVE is not implemented or the PE is in Streaming SVE mode, and instructions that directly access the <a href="AArch64-svcr.html">SVCR</a>, <a href="AArch64-smcr_el1.html">SMCR_EL1</a>, or <a href="AArch64-smcr_el2.html">SMCR_EL2</a> System registers to EL2, when EL2 is enabled in the current Security state.</p>
<p>When instructions that directly access the <a href="AArch64-svcr.html">SVCR</a> System register are trapped with reference to this control, the <span class="instruction">MSR SVCRSM</span>, <span class="instruction">MSR SVCRZA</span>, and <span class="instruction">MSR SVCRSMZA</span> instructions are also trapped.</p>
<p>The exception is reported using ESR_EL2.EC value of <span class="hexnumber">0x1D</span>, with an ISS code of <span class="hexnumber">0x0000000</span>.</p>
<p>This field does not affect whether Streaming SVE or SME register values are valid.</p>
<p>A trap taken as a result of CPTR_EL2.TSM has precedence over a trap taken as a result of CPTR_EL2.TFP.</p><table class="valuetable"><tr><th>TSM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause execution of any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-12_12-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_1-11_11">Bit [11]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-10_10">TFP, bit [10]</h4><div class="field"><p>Traps execution of instructions which access the Advanced SIMD and floating-point functionality, from both Execution states to EL2, when EL2 is enabled in the current Security state, as follows:</p>
<ul>
<li>In AArch64 state, accesses to the following registers are trapped to EL2, reported using ESR_ELx.EC value <span class="hexnumber">0x07</span>:<ul>
<li><a href="AArch64-fpcr.html">FPCR</a>, <a href="AArch64-fpsr.html">FPSR</a>, <a href="AArch64-fpexc32_el2.html">FPEXC32_EL2</a>, any of the SIMD and floating-point registers V0-V31, including their views as D0-D31 registers or S0-31 registers.
</li></ul>

</li><li>In AArch32 state, accesses to the following registers are trapped to EL2, reported using ESR_ELx.EC value <span class="hexnumber">0x07</span>:<ul>
<li><a href="AArch32-mvfr0.html">MVFR0</a>, <a href="AArch32-mvfr1.html">MVFR1</a>, <a href="AArch32-mvfr2.html">MVFR2</a>, <a href="AArch32-fpscr.html">FPSCR</a>, <a href="AArch32-fpexc.html">FPEXC</a>, and any of the SIMD and floating-point registers Q0-15, including their views as D0-D31 registers or S0-31 registers.
For the purposes of this trap, the architecture defines a VMSR access to <a href="AArch32-fpsid.html">FPSID</a> from EL1 or higher as an access to a SIMD and floating-point register. Otherwise, permitted VMSR accesses to <a href="AArch32-fpsid.html">FPSID</a> are ignored.
</li></ul>

</li></ul>
<p>Traps execution at the same Exception levels of 
SME and 
SVE instructions 
 to EL2, when EL2 is enabled in the current Security state.
The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x07</span>.</p>
<p>A trap taken as a result of CPTR_EL2.TSM has precedence over a trap taken as a result of CPTR_EL2.TFP.</p>
<p>A trap taken as a result of CPTR_EL2.TZ has precedence over a trap taken as a result of CPTR_EL2.TFP.</p><table class="valuetable"><tr><th>TFP</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause execution of any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p><a href="AArch64-fpexc32_el2.html">FPEXC32_EL2</a> is not accessible from EL0 using AArch64.</p>
        <p><a href="AArch32-fpsid.html">FPSID</a>, <a href="AArch32-mvfr0.html">MVFR0</a>, <a href="AArch32-mvfr1.html">MVFR1</a>, and <a href="AArch32-fpexc.html">FPEXC</a> are not accessible from EL0 using AArch32.</p>
      </div>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-9_9">Bit [9]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_1-8_8-1">TZ, bit [8]<span class="condition"><br/>When FEAT_SVE is implemented:
                        </span></h4><div class="field"><p>Traps execution at EL2, EL1, and EL0 of SVE instructions when the PE is not in Streaming SVE mode, and instructions that directly access the <a href="AArch64-zcr_el2.html">ZCR_EL2</a> or <a href="AArch64-zcr_el1.html">ZCR_EL1</a> System registers to EL2, when EL2 is enabled in the current Security state.</p>
<p>The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x19</span>.</p>
<p>A trap taken as a result of CPTR_EL2.TZ has precedence over a trap taken as a result of CPTR_EL2.TFP.</p><table class="valuetable"><tr><th>TZ</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause execution of any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-8_8-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_1-7_0">Bits [7:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing CPTR_EL2</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, CPTR_EL2</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0001</td><td>0b0001</td><td>0b010</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TCPAC == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        X[t, 64] = CPTR_EL2;
elsif PSTATE.EL == EL3 then
    X[t, 64] = CPTR_EL2;
                </p><h4 class="assembler">MSR CPTR_EL2, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0001</td><td>0b0001</td><td>0b010</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TCPAC == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        CPTR_EL2 = X[t, 64];
elsif PSTATE.EL == EL3 then
    CPTR_EL2 = X[t, 64];
                </p><h4 class="assembler"><span class="condition">
When FEAT_VHE is implemented
            </span><br/>MRS &lt;Xt&gt;, CPACR_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b0001</td><td>0b0000</td><td>0b010</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TCPAC == '1' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; CPTR_EL2.TCPAC == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HFGRTR_EL2.CPACR_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV1,NV&gt; == '111' then
        X[t, 64] = NVMem[0x100];
    else
        X[t, 64] = CPACR_EL1;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TCPAC == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HCR_EL2.E2H == '1' then
        X[t, 64] = CPTR_EL2;
    else
        X[t, 64] = CPACR_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = CPACR_EL1;
                </p><h4 class="assembler"><span class="condition">
When FEAT_VHE is implemented
            </span><br/>MSR CPACR_EL1, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b0001</td><td>0b0000</td><td>0b010</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TCPAC == '1' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; CPTR_EL2.TCPAC == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HFGWTR_EL2.CPACR_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV1,NV&gt; == '111' then
        NVMem[0x100] = X[t, 64];
    else
        CPACR_EL1 = X[t, 64];
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TCPAC == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HCR_EL2.E2H == '1' then
        CPTR_EL2 = X[t, 64];
    else
        CPACR_EL1 = X[t, 64];
elsif PSTATE.EL == EL3 then
    CPACR_EL1 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
